1. Field of the Invention
This invention relates to spatial light modulators, more particularly to memory schemes supporting spatial light modulator arrays.
2. Background of the Invention
In one form, spatial light modulators consists of an array of individually addressable elements, such as liquid crystal display panels or digital micromirror devices. These examples of modulator arrays have many uses, such as printers, displays, and optical processing. This discussion will focus on display systems.
In some applications, these arrays function in binary mode, where each individual element receives either an ON or an OFF signal. Typically, the elements, or pixels, of the array that receive the ON signal form the image the viewer receives, either directly, from a screen or through optics.
To individually address each pixel, each modulator array must have circuitry allowing signals to reach each pixel and activate it to respond in a certain way. One approach requires one memory cell per pixel, where the memory cell receives the information for the pixel's next state. This information results from the scheme used to produce the displayed images.
One technique for production of images, called pulse width modulation, has each pixel turn ON and OFF repeatedly within a video frame time. This method controls the intensity of a given pixel by how many times within the frame the pixel is ON, or transmitting light to the final image. Digitally, gray levels are achieved by using weighted bits of data.
For example, to achieve 16 gray levels, each pixel receives 4 bits of data over the time period of one frame. The frame time is divided into 15 slices, 1-15. The most significant bit (MSB) would then receive 8 of those time slices for it to display its data. The next most significant bit would receive 4, etc. Techniques exist that allow these time slice to be assigned to the bits of data in non-contiguous sections. For example, the MSB may be displayed for 2 time slices at once, then be displayed for the other 6 time slices at another time, or even be divided up again. A detailed description of this method using the DMD as an example is in U.S. Pat. No. 5,278,652, "DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System."
The above technique requires memory for keeping the data to be displayed and sending it to the pixel at the appropriate time. One technique uses one memory cell per pixel. The cell receives the pixel's data, the pixel gets a control signal allowing it to react to the new data is latched into its new state. Meanwhile, the cell is receiving the data for the pixel's next state. When the pixel transfer signal occurs, the pixel reacts to its new data.
The above described method focuses on an entire array receiving the pixel transfer signal at once. However, techniques exist that allow any one pixel to receive the transfer signal by itself. This allows for a much lower data rate making the system much more manageable. One such method is discussed in U.S. patent application Ser. No. 08/002,627, "Pixel Control Circuitry for Spatial Light Modulator."
This particular technique, often referred to as split reset, uses less than one memory cell per pixel, with tile number of pixels per memory cell called "fanout." This architecture will be referred to more accurately as a multiplexed memory architecture. The memory cell receives the data for a set of pixels, rather than just one. To have the peak data rate most closely match the average data rate, the fanout is calculated as: ##EQU1## where n=the number of bits of intensity. Therefore, if 4 bits of intensity were desired, there would be a fan out of 2.sup.4 -1, or 15, divided by 4, equalling 3.75 pixels. Since fractional pixels are impossible, there would be 4 pixels per memory cell.
One problem with the above approach is that the number of levels of intensity is linked to the number of pixels per memory cell. The number of pixels per memory cell must be determined before the device is fabricated. Using a device with a set fanout for a different number of bits of intensity increases the data rate, which eliminates the main advantage of using multiplexed memory architecture.
Therefore, if the number of levels of intensity is different, different devices need to be fabricated to keep system costs down. A need exists for a method that makes the multiplexed memory architecture scheme more flexible and eliminates the need for specially fabricated devices.